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IRS20955(S)PbF
4. P LSH : Power Dissipation of the High-Side
Level Shifter
P LSH = 0.4 nC x f sw x V BUS
where
f SW = the PWM switching frequency
V BUS = the difference between the positive bus
voltage and negative bus voltage
Total power dissipation, P d , is given by
P d = P MID + P LSM + P LOW + P HSM + P HIGH .
Given R th,JA , the thermal resistance between the
ambient and junction temperature, T J , the junction
temperature, can be calculated from the formula
provided below.
T J = R th , JA ? P d + T A < 150 ° C
5. P HIGH : Power Dissipation in High-side
The power dissipation in high-side comes from
the losses of the logic circuitry and the losses of
driving LO.
P HIGH = P LDD + P HO
= ( I QBS ? V BS ) + ? V BS ? Q g ? f SW ?
?
?
?
?
?
R O
R O + R g + R g (int) ? ?
where
P LDD = the power dissipation from the internal
logic circuitry
P LO = the power dissipation from the gate drive
stage to HO
R O = equivalent output impedance of HO,
typically 10 ? for the IRS20955S
R g(int) = the internal gate resistance of the high-
side MOSFET driver, typically 10 ? for the
IRS20955S
R g = external gate resistance of the high-side
MOSFET
Q g = total gate charge of the high- side
MOSFET
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